www.iterrac.com IT4021D 20 gb/s (12.5 gb/s rz) t-type flip-flop (advanced information) this is an advanced data sheet. see product status definitions on web site or catalog for product development stat us. april 24, 2007 doc. 4049 rev 1.0 1 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 description features the IT4021D is a high-speed t-type flip-flop fabric ated using 1 m hbt gaas technology. the t flip-flop consists of a master-slave latch, close d-in feedback, and is designed using an ecl topology in order to guarantee high-speed operation . the data input may be either ac or dc coupled, the output is dc coupled. at the input sid e the internal 50-ohm resistors avoid the need for external terminations for impedance matchi ng. the IT4021D uses scfl i/o levels and is designed to allow for either single-ended or differential data input/output. an on-chip, output buffer produces an excellent eye diagram up to an output rate of 12.5 gb/s rate (20 gb/s nrz or 12.5 gb/s rz input data rate) or 14 ghz input clock. the high output voltage, excellent rise and fall times, and the high-qualit y eye diagram at all clock frequencies makes the IT4021D suitable for very-high-speed, complex d igital applications such as differential encoding, clock dividers, and edge detectors. data rate range: 20 nrz (12.5 rz) gb/s maximum clock frequency as clock divider: 14 ghz 900 mvpp typical single-ended output input sensitivity: single ended input >250 mv jitter transfer rms: <1 ps output rise time (20% - 80%): <27 ps device diagram timing diagram output fall time (20% - 80%): <24 ps dc or ac coupled data input 50-ohm matched dc-coupled data output differential or single-ended inputs and outputs full scfl i/o level compatibility low power consumption: 0.71 w
www.iterrac.com IT4021D 20 gb/s (12.5 gb/s rz) t-type flip-flop (advanced information) this is an advanced data sheet. see product status definitions on web site or catalog for product development stat us. april 24, 2007 doc. 4049 rev 1.0 2 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 absolute maximum ratings recommended operational conditions c 150 -65 storage temperature tstg c 125 -15 operating temperature range C die ta v 1.2 -1.2 data/clock input voltage level, low level vdl v 1.2 -1.2 data/clock input voltage level, high level vdh v 0 -5.5 power supply voltage vee units max min. parameters/conditions symbol v 0.5 data/clock input voltage level (single-ended peak t o peak) vipp v 0 -0.3 dc input voltage (with dc-coupled input) vindc v -0.25 -0.6 data/clock input voltage level, low level (single e nded) vdl v 0.25 -0.1 data/clock input voltage level, high level (single ended) vdh v -5.2 power supply voltage vee c 85 0 operating temperature range C die ta units max typ min. parameters/conditions symbol ghz 14 12.5 0 clock frequency as a clock divider (4) fmax ps 145 135 125 input to data output delay (3) tdl ps 24 output fall time (20% - 80%) tf ps 27 output rise time (20% - 80%) tr v -0.85 -0.9 -0.95 data output voltage amplidude low vql v 0 0 -0.05 data output voltage amplidude high vqh v 0.25 0 -0.75 dc input voltage (with dc-coupled input) (2) vindc 1.8 1.0 0.50 data/clock input voltage level differential peak to peak vindiffpp v 0 -0.25 -1 data/clock input voltage level, low level (single ended) vdl v 0.5 0.25 -0.5 data/clock input voltage level, high level (single ended) vdh v -4.85 -5.2 -5.45 power supply voltage vee units max typ min parameters symbol electrical characteristics 1. electrical characteristics at ambient temperature. 2. in case of single-ended inputs, the unused ones must be tied to vindc which must be set close to the mean value of the used one. 3. output change state on input rising edge. 4. duty cycle 50%. asymmetrical duty cycle may reduce maximum toggling frequency. 25 gb/s input working data rate is possible tolerating additional jitter degradations. stresses in excess of those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions above those indicated in the operational section of this document is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
www.iterrac.com IT4021D 20 gb/s (12.5 gb/s rz) t-type flip-flop (advanced information) this is an advanced data sheet. see product status definitions on web site or catalog for product development stat us. april 24, 2007 doc. 4049 rev 1.0 3 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 w 0.71 power dissipation pd ma 136 power supply current ic ps 1.3 rms jitter jrms ps 9 8 7 peak to peak jitter jpp ps 40 minimum pulse width mpw db 5.5 minimum output return loss (up to 15 ghz) rlout db 20 minimum input return loss (up to 15 ghz) rlin gb/s 20 (-25) 12.5 0 input data rate (4) rmax units max typ min parameters symbol electrical characteristics (cont.) eye diagram performance test board measurement vee: -5.2 v rz input rate: 12.5 gb/s (duobinary pre coder application) single-ended data input (0,-900 mvpp) dc coupled left: time domain (fixed pattern) right : eye di agram (pn pattern) upper signal: rz input lower signal: duobinary pr ecoded output for duobinary use tff in single-ended input and tu ne vindc on unused input. die measurement vee: -5.2 v nrz input rate: 12.5 gb/s single-ended data input: +/-250 mvpp die measurement vee: -5.2 v + 5% = -4.95 v clock: 12.5 ghz single-ended data input: +/-450 mvpp
www.iterrac.com IT4021D 20 gb/s (12.5 gb/s rz) t-type flip-flop (advanced information) this is an advanced data sheet. see product status definitions on web site or catalog for product development stat us. april 24, 2007 doc. 4049 rev 1.0 4 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 eye diagram performance (cont.) recommended operational setup 1. electrical characteristics at ambient temperature. 2. in case of single-ended inputs, the unused ones must be tied to vindc which must be set close to the mean value of the used one. 3, output change state on input rising edge. 4. duty cycle 50%. asymmetrical duty cycle may reduce maximum toggling frequency. die measurement vee: -5.2 v clock frequency: 12.6 ghz single-ended clock input: +/-450 mvpp die measurement vee: -5.2 v clock frequency: 10.709 ghz single-ended clock input: +/-450 mvpp die measurement vee: -5.2 v clock frequency: 5.0 ghz single-ended clock input: +/-450 mvpp die measurement vee -5.2. v clock frequency: 1.0 ghz single-ended clock input: +/-450 mvpp
www.iterrac.com IT4021D 20 gb/s (12.5 gb/s rz) t-type flip-flop (advanced information) this is an advanced data sheet. see product status definitions on web site or catalog for product development stat us. april 24, 2007 doc. 4049 rev 1.0 5 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 recommended chip mounting pad positions and chip dimensions chip size: 1600 m 10 m x 2000 m 10 m edge to edge chip thickness: 104 m 3 m pad size: 100 m x 100 m rf pad pitch: 150 m unlabeled pads are ground and may be left floating
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